1. Field of the Invention
The present invention relates to a method for testing a USB (universal serial bus) device, and more particularly, to a method and system for testing a USB device by converting a USB packet trace output from a USB host to a host model code.
2. Description of Related Art
To analyze and correct an error generated in a USB SoC (system on chip) device, an RTL (register transfer level) of the USB SoC device is checked by assuming where the error is generated and testing the USB SoC device by generating a FPGA (field programmable gate array) and connecting the FPGA to an actual USB host.
A method using the RTL may check the internal signal and status of the device. However, it is difficult to assume where the error has occurred and reproduce or analyze the cause of the error given an incorrect assumption. Further, the method can reproduce the same error status because the host situation is the same. However, substantially time and effort is needed to correct the error because the internal signal assumed to be relevant is generated as an external output to check the internal status of the device, and the FPGA corresponding to the external output needs to be repeatedly generated.
Thus, there is a demand for a method and apparatus which can reproduce an error of an actual situation and simulate the same internal signal and device status as those in an RTL/NET (netlist: gate level) simulation.